In the fabrication of semiconductor devices there is an on-going need to reduce packaging costs and improve the electrical and thermal performance of the packages. Package sizing is also important especially the profile or height of the package when mounted to a printed wiring board or printed circuit board. Semiconductor manufacturers continue to develop low profile packages in order to satisfy user requirements for circuit boards having a thin profile when fully populated by semiconductor devices. Complicating the situation is the increasing complexity of electronic components such as integrated circuits which require a high package pin count to electrically connect the device to a user system.
Many of the foregoing requirements can be satisfied by a semiconductor device having a plastic pad array carrier package. The pad array carrier is a surface mount device having a low profile, high pin count and can be fabricated in plastic which offers a cost savings compared to other high pin count package materials such as ceramic and the like. Pad array carriers can address many of the current needs in device packaging but face limitations in heat dissipation. Development of improved heat dissipation characteristics and optimized package lead designs can enhance the ability of semiconductor devices having plastic pad array carrier packages to address industry requirements for low cost, high performance VLSI devices.